Taiwan Semiconductor Manufacturing Company (TSMC) has unveiled early details of its next-generation 1.4 nm Gate-All-Around (GAA) process, aiming to commence high-volume manufacturing by 2028. Following the successful rollouts of 3 nm in 2022 and 2 nm GAA in pilot this year, the 1.4 nm node represents yet another leap in transistor density, power efficiency, and performance per watt. By further wrapping the transistor channel in nanosheet gate material, TSMC intends to push silicon scaling toward its physical limits, enabling breakthroughs in artificial intelligence, high-performance computing, mobile devices, and beyond. This article explores the technical innovations underpinning the 1.4 nm node, the milestones along TSMC’s development roadmap, manufacturing challenges and ecosystem readiness, anticipated applications and impact across industries, and the broader context of Moore’s Law as it nears atomic-scale dimensions.
Evolution from FinFET to Gate-All-Around: The Road to 1.4 nm
Semiconductor scaling has followed a continuous trajectory since the 1960s, but ever-shrinking feature sizes have required successive transistor architectures. Planar transistors gave way to FinFETs at the 22 nm node, using thin vertical fins to improve gate control. As dimensions fell below 7 nm, even FinFET’s three-sided gate control proved insufficient to contain leakage and variability. To overcome these limitations, TSMC pioneered GAA nanosheet transistors at 3 nm, wrapping the gate material fully around multiple stacked channels. The 2 nm node in pilot production refines this design, narrowing nanosheet thickness and optimizing gate-alloy work functions. The upcoming 1.4 nm node pushes these concepts further: transistor channels will be etched down to atomic-scale thicknesses (sub-2 nm wide), with novel high-k metal gate materials and spacer-on-spacer patterning. This evolution enhances electrostatic control, reduces short-channel effects, and allows even lower supply voltages—key for cutting power consumption in the AI accelerators and system-on-chip designs that define modern computing workloads.
Key Innovations in the 1.4 nm GAA Process
Realizing a 1.4 nm GAA process requires breakthroughs across lithography, materials, and device integration. First, TSMC will leverage next-generation high-NA EUV lithography tools capable of sub-8 nm patterning in a single exposure, minimizing reliance on multi-patterning. Second, new gate-alloy stacks—combining ultra-thin hafnium-based dielectrics with cobalt-tungsten liners—ensure minimal leakage at scaled dimensions. Third, the process introduces a novel multi-layer spacer-on-spacer etch, enabling precise control of nanosheet thickness and uniformity across the wafer. Fourth, cobalt and ruthenium metal interconnects replace copper in the most critical layers to reduce resistivity at sub-20 nm pitches. Fifth, advanced strain-engineering techniques embed silicon-germanium stressors in the channel to boost carrier mobility. Together, these innovations yield projected improvements of 20–25 percent in performance per watt versus 2 nm, and over 60 percent increase in transistor density—equivalent to more than 2.5 trillion transistors on a single large-format wafer.
Development Roadmap and Pilot Production Milestones
TSMC’s 1.4 nm development began in late 2023, building on experience from its Nanjing R&D facility and Hsinchu’s pilot lines. In 2024, the company completed integration of high-NA EUV scanners at Fab 18 and demonstrated sub-10 nm metal patterns at pilot scale. By mid-2025, test wafers featuring early nanosheet stacks achieved functional transistor arrays with sub-50 mV/decade subthreshold swings, confirming the viability of ultra-thin channels. In 2026, TSMC plans volume pilot runs—processing hundreds of wafers per month—to refine yield and uniformity, collaborating with equipment partners to tune etch and deposition recipes. A late-2027 tape-out window will enable early customer designs, giving major chipmakers time to validate IP and libraries. High-volume manufacturing is slated for Q2 2028 at Fab 18’s expanded facilities, complemented by capacity at the forthcoming Arizona campus for select customers. By staggering ramp across multiple fabs, TSMC aims to meet demand for flagship mobile SoCs, AI accelerators, and high-end datacenter processors without supply shocks.
Manufacturing Challenges and Ecosystem Readiness
Scaling to 1.4 nm confronts formidable challenges. Achieving atomic-level thickness control of nanosheets demands sub-angstrom uniformity, pushing metrology tools to their limits. High-NA EUV pellicles and photoresists must endure billions of shots with minimal defectivity. Interconnect reliability at pitches below 20 nm requires new barrier materials and advanced electromigration testing. Thermal budgets tighten, as high-temperature steps can trigger dopant diffusion and structure collapse. To surmount these hurdles, TSMC is co-engineering solutions with ASML, Applied Materials, Lam Research, and other key equipment vendors. Concurrently, EDA partners are enhancing simulation models to capture quantum confinement effects and variability at atomic scales. IP vendors—providing standard cell libraries and memory compilers—are already developing design kits fine-tuned for GAA characteristics. Wafer-level packaging innovations, including CoWoS-3D stacking and advanced fan-out, are being qualified in parallel to ensure high-performance packaging that complements the transistor advances. The industry’s collective readiness will determine how swiftly 1.4 nm transitions from pilot to production.
Anticipated Applications and Industry Impact
The 1.4 nm GAA node will underpin the next wave of computing breakthroughs. In artificial-intelligence and machine-learning accelerators, the performance-per-watt gains enable larger model inference at datacenter scale without proportionate increases in power draw. Mobile SoCs leveraging 1.4 nm will deliver up to 30 percent faster CPU and GPU speeds while extending smartphone battery life. High-performance computing and network-edge devices will benefit from reduced die sizes for a given compute power, lowering system cost and enabling denser rack-level deployments. Specialized markets—such as automotive L4/L5 autonomy, real-time signal processing, and AR/VR headsets—will see new levels of integration and efficiency. Moreover, the sheer transistor density opens possibilities for novel heterogeneous integration on a single chip, merging AI cores, CPU clusters, DSPs, and memory in unprecedented configurations. As chipmakers harness 1.4 nm, barriers between application domains will blur, driving cross–industry innovation and reinforcing TSMC’s leadership in foundry technology.
Moore’s Law in the Atomic Era: Looking Beyond 1.4 nm
The successful deployment of 1.4 nm GAA will mark one of the last steps in classical transistor scaling before atomic and quantum effects dominate. Beyond this node, TSMC and the broader industry are already exploring alternative paradigms: monolithic 3D integration to stack logic layers vertically; gate-all-around nanowires at sub-1 nm widths; novel channel materials like germanium or III-V compounds for higher mobility; and cryogenic CMOS for quantum-classical co-processors. Process complexity and cost per wafer will continue to rise, prompting a shift toward chiplet-based architectures and heterogeneous packaging, where specialized dies—fabricated at different nodes or with disparate technologies—are united in a single multi-chip module. In this context, 1.4 nm GAA serves both as a pinnacle of silicon scaling and as a bridge to post-Moore approaches. By pushing silicon to its limits while orchestrating next-generation integration techniques, TSMC ensures that the semiconductor roadmap remains vibrant, adaptable, and poised to meet the insatiable demands of future compute workloads.